NVIDIA has formally announced that co-packaged optics (CPO) has entered the mass-production stage, with related products being delivered to key customers. Spurred by the news, A-share optical-communications stocks surged across the board, giving the market a clear signal that the commercialization inflection point for next-generation co-packaged optics has arrived.
As bandwidth demand from AI compute clusters explodes, conventional pluggable optical modules are gradually approaching physical limits in power consumption, density, and signal loss. Represented by CPO, co-packaged optical interconnects shorten the electro-optical path to deliver higher bandwidth density and lower system power, and have become a core technology pathway for intelligent computing clusters at the scale of tens of thousands—or even hundreds of thousands—of accelerators. Overseas industry leaders have already demonstrated mature architectures and production-ready solutions. For the domestic industry, however, the CPO boom is not simply a race to catch up with a single product: the real breakthrough challenge lies in localizing the full stack—underlying architectures, chips, packaging, and optical-mechanical systems.
Source: [1] Yole Group, Co-Packaged Optics for Data Centers 2025, June 2025.
Why Are Optical Engines Moving Closer to the Chip?
Traditional pluggable optical modules are deployed on the front panel of switching equipment and connect to switch ASICs or compute chips via high-speed electrical signals on the motherboard. They offer maturity, standardization, and hot-pluggability, yet as per-lane rates and switch capacity continue to rise, ever-longer high-speed electrical traces incur greater signal loss, higher power consumption, and more complex system design.
NPO—near-packaged optics—moves the optical engine closer to the switch or compute chip, shortening board-level electrical interconnects.
CPO goes a step further by integrating the optical engine with the host chip within the same packaging system, so that electro-optical conversion occurs inside or at the edge of the package.
At the OIO (optical I/O) stage, the optical engine further becomes an optical I/O chiplet of the compute system, and the boundary between optical interconnect and the compute chip begins to blur.
These four form factors are not simply successive replacements for one another; rather, they correspond to different trade-offs among integration density, cost, serviceability, and application scenarios. Their shared direction is to shorten the distance traveled by high-speed electrical signals and to hand data transmission over to optics earlier.
Source: [2] Minkenberg et al., IET Optoelectronics, 2021
How NPO/CPO/OIO Differ from Conventional Optical Modules
As demand from AI foundation models and high-performance computing grows exponentially, the power and bandwidth of conventional electrical interconnects are approaching physical limits. CPO (co-packaged optics) and OIO (optical I/O) have therefore become critical pathways for breaking through compute bottlenecks.
Their core value is first reflected in high bandwidth density: by substituting optics for electronics, CPO/OIO fundamentally break the physical pin-density constraints at the traditional chip beachfront, enabling massive throughput of hundreds of Gbps per lane—and overall Tbps-class capacity—within a very small footprint. To sustain such extreme data-exchange efficiency, electro-optical co-design becomes inevitable. It deeply co-optimizes photonic integrated circuits (PICs) with electronic integrated circuits (EICs) responsible for drive and receive functions, avoiding the severe attenuation and signal-integrity issues associated with long-reach electrical transmission in conventional pluggable modules, and substantially reducing overall system power.
To achieve extreme electro-optical integration, 3D packaging is indispensable. Conventional 2D or 2.5D side-by-side layouts still leave interconnect paths relatively long, whereas 3D advanced packaging approaches—such as through-silicon vias (TSVs), micro-bumps, or copper–copper hybrid bonding—enable vertical stacking of photonic chips, electronic chips, and core compute chips (ASICs/GPUs). This three-dimensional integration compresses physical interconnect distances between electro-optical nodes from the centimeter scale to the micrometer scale, minimizing parasitic capacitance and inductance. It not only delivers ultra-low communication latency and pJ/bit-class energy efficiency, but also constitutes a critical technological foundation for future 100-megawatt-class hyperscale compute clusters.
Source: [3] SemiAnalysis
Where Do the Real Challenges of CPO and OIO Lie?
Placing the optical engine next to the chip is only the first step. To ach
First, domestic electro-optical integration—especially advanced packaging—is still at an early exploratory stage.
The PIC handles optical modulation and transmission, while the EIC provides high-speed drive and signal processing. The longer the interconnect between them, the harder it becomes to control parasitics, signal loss, and energy consumption. To further raise per-lane rates and bandwidth density, the EIC and PIC must be brought closer together—hence the need for 3D advanced packaging.
Domestic capabilities in 3D advanced packaging technologies such as TSVs and copper–copper hybrid bonding, as well as joint electro-optical design and packaging, remain at the exploratory and proof-of-concept stage.
Second is optical coupling and wafer-level testing.
Coupling light from a silicon-photonic chip into optical fiber requires reducing insertion loss while controlling wavelength, polarization, process variation, and assembly tolerance. For advanced optical engines, merely demonstrating that “a single sample works” is far from sufficient: high-efficiency testing and screening must be completed at the wafer stage to prevent defective dies from entering costly downstream packaging. Only by securing yield and reliability through semiconductor manufacturing practices can true mass production be achieved.
Third is balancing integration density with serviceability.
Once the optical engine enters the package, system bandwidth density and energy efficiency improve, but fiber attach, laser sources, thermal management, reliability, and subsequent operations and maintenance become more complex. CPO and OIO are not merely chip problems; they are system-engineering challenges spanning optics, electronics, thermal and mechanical design, and packaging. Optical-engine vendors must deliver not only chiplets, but also reliable system-level solutions.
Fourth is supply-chain resilience.
CPO and OIO span advanced-process chips, silicon-photonic devices, advanced packaging, fiber coupling, and precision test equipment. The supply chain is broad and coordination-intensive; combined with limited fab and OSAT capacity and long-standing shortages of materials such as high-frequency substrates, a breakdown at any single node can disrupt production schedules.
TSMC’s COUPE: One Answer to the Challenge
COUPE stands for Compact Universal Photonic Engine.
Its value lies not merely in a single silicon-photonic chip, but in a complete integration architecture spanning the PIC, EIC, advanced packaging, and fiber interfaces.
First, through SoIC-X 3D stacking, COUPE places the EIC atop the PIC, compressing critical electro-optical chip interconnects from board-level scales to 3D-package scales. This reduces interface impedance and parasitics, creating headroom for higher bandwidth density and lower transmission power.
Second, for grating couplers (GCs), COUPE builds a vertical optical path incorporating microlenses, reflective structures, and anti-reflection design. Published results show that its GCs can maintain low insertion loss on COUPE wafers and support wafer-level optical, electrical, and reliability testing and characterization—indicating that optical interfaces are beginning to acquire test-and-screen capabilities commensurate with semiconductor manufacturing.
Third, by forming an expand–collimate–refocus optical path with chip-side microlenses and connector-side lenses, the approach reduces the assembly difficulty of aligning fiber directly to a tiny optical spot and lays the foundation for detachable, pluggable optical interfaces.
These three capabilities address three critical questions, respectively: how to shorten electro-optical chip interconnects; how to verify optical performance at the wafer stage; and how optical paths entering the package can balance assembly with maintainability. The fourth challenge—supply-chain resilience—falls outside the primary concern of a company of TSMC’s scale.
TSMC has publicly stated that CPO solutions based on COUPE on substrate are planned to enter production in 2026; relative to board-level pluggable approaches, stated targets include a 2× improvement in power efficiency and a 90% reduction in latency. COUPE is therefore not merely a device technology, but a system roadmap linking silicon photonics, advanced packaging, and high-performance computing.
Source: [4] TSMC, IEEE ECTC 2025
Following the same path, Nvision is building a domestic technology platform.
Nvision’s goal is to work with industry partners to build a domestic supply-chain ecosystem and to be among the first in mainland China to realize an electro-optical integration pathway sharing the same core logic as COUPE. To that end, Nvision has never treated PICs, NPO, CPO, and OIO as isolated products; instead, it is building an optical-engine technology platform capable of continuous evolution.
At the present stage, one of the NPO solutions Nvision is advancing adopts a core optical-path architecture consistent with COUPE. Around this solution, Nvision has established end-to-end in-house capabilities spanning silicon-photonic chips, advanced packaging, high-speed substrate design, and optical-mechanical structure design—delivering semiconductor-centric optical-engine solutions to optical-module vendors, GPU vendors, switch vendors, and system customers.
Placing TSMC’s COUPE alongside Nvision’s current NPO solution reveals a highly consistent core logic at the optical interface: vertical out-coupling via the GC → chip-side microlens beam shaping → free-space beam expansion → FAU-side lens focusing → mirror turn → coupling into the fiber array.
This means Nvision’s current NPO solution is not merely an interim product, but can also serve as an engineering validation platform for future CPO. Capabilities accumulated today in GC design, microlenses, FAUs, optical-mechanical assembly, wafer testing, and reliability can continue to migrate into single-wavelength 200G and 3D-packaged optical engines, as well as subsequent CPO/OIO solutions.
Nvision Optical Path
Source: [4] TSMC, IEEE ECTC 2025
Looking ahead, for NPO/CPO, Nvision is developing single-wavelength 200G and 3D heterogeneously integrated optical engines to further raise bandwidth density and shorten critical interconnect paths.
On the more forward-looking OIO front, Nvision is also advancing micro-ring modulator solutions and has achieved positive interim results. Micro-rings offer small footprint, low power, and strong potential for dense wavelength-division multiplexing, aligning closely with the trajectory of next-generation high-density, low-power, multi-wavelength optical I/O. Yet they impose stricter requirements on process control, temperature management, packaging, and light sources—precisely where chip–system co-design capability is essential.
What Nvision seeks to accomplish is not the replication of any single product form factor, but the integration of silicon-photonic chips, electro-optical co-design, 3D advanced packaging, and a domestic supply chain into a platform capable of continuous upgrades.
Three Chips, One System
From a systems perspective, future AI compute infrastructure can be understood as three critical building blocks: GPUs/ASICs for computation, HBM for high-bandwidth data supply, and CPO/OE optical engines for high-speed communication. Compute sets the ceiling on processing power; HBM determines data-feeding capacity; and the optical engine determines the scale of compute connectivity.
Through its advanced packaging technology portfolio, TSMC is driving deeper convergence among compute chips, HBM, and optical interconnects. We believe this will become a major mainstream direction for next-generation AI compute infrastructure.
Nvision has chosen to advance along this path: starting from NPO/CPO and continuously evolving toward OIO; beginning with self-developed silicon-photonic chips to build an end-to-end silicon-photonics process platform; breaking through in 3D advanced packaging; and co-building a domestic supply chain with ecosystem partners. Our goal is clear—to become among the first companies in mainland China to deliver a COUPE-aligned electro-optical integration architecture on a domestic supply chain.
Bring light closer to the chip—and integrate domestic optical engines into next-generation compute systems.
Sources:
[1] Yole Group, “Co-Packaged Optics for Data Centers 2025,” Yole Intelligence Market Report, June 2025.
[2] C. Minkenberg, R. Krishnaswamy, A. Zilkie, and D. Nelson,
“Co-packaged Datacenter Optics: Opportunities and Challenges,”
IET Optoelectronics, vol. 15, no. 2, pp. 77–91, 2021.
[3] D. Patel, D. Nishball, M. Xie et al.,
“Co-Packaged Optics (CPO) Book – Scaling with Light for the Next Wave of Interconnect,”
SemiAnalysis Research Report, Jan. 2026.
[4] M. F. Chen, H. T. Cheng, C. H. Tsou, S. Y. Hou, T. H. Yu,
S. Liu, R. Lu, and K. C. Hsu,
“Optical and Electrical Characterization of a Compact Universal Photonic Engine,”
2025 IEEE 75th Electronic Components and Technology Conference (ECTC),
pp. 54–58, 2025, doi: 10.1109/ECTC51687.2025.00015.
