September 8, 2026 — FiberOnline News. "Interconnect has become the bottleneck for next-generation AI intelligent computing. Using optical engine I/O to interconnect computing and memory chips, and reducing latency and power consumption through optoelectronic convergence, have become key priorities for computing-power networks under the 15th Five-Year Plan. OIO (Optical I/O) will necessarily mean heterogeneous and hybrid-integrated optical interconnect — reconstructing optical interconnect with a semiconductor Moore's Law mindset," said Dr. Nie Hui, founder of NVISION (Yingweixin), in a recent interview with FiberOnline.
Nie Hui previously led Intel's silicon photonics program from design through volume production. At the end of 2024, he and his team founded NVISION Technology in Xi'an, with a clear positioning: an OIO full-stack solution based on domestically grounded wafer-level optoelectronic hybrid/heterogeneous integration plus advanced packaging.
Against a crowded NPO/CPO/OIO landscape, what allows NVISION to enter the market quickly and roll out five silicon-photonics chip solutions? How do the NPO, CPO, and OIO technology paths relate? Where is the domestic gap, and where are the shortfalls? With these questions, we interviewed NVISION founder Dr. Nie Hui at this year's CIOE.
NVISION's Positioning: Why Wafer-Level Heterogeneous Integration?
Nie Hui's own career is a microcosm of the silicon photonics industry. Recommended for admission to the Physics Department of the University of Science and Technology of China (USTC), he earned a Ph.D. in electrical engineering from the University of Texas at Austin, focusing on high-performance photodetectors. He then spent seven years at Lucent Bell Labs developing optoelectronic devices and lived through a full cycle of the optical communications industry in telecom transmission markets. After joining Intel in 2015, he led the world's first low-cost heterogeneously integrated silicon photonics product into volume production — a program that cumulatively shipped more than 8 million fully integrated silicon photonic chips.
Returning to China in 2019, he joined a leading LiDAR startup and led a team that, relying on the domestic supply chain, cut LiDAR device cost to one-tenth of its previous level while improving performance by tens of times. At the end of 2024, he founded NVISION.
"At the outset of entrepreneurship, we saw that large-scale data centers were continuing to be built and deployed — a highly certain industry trend," Nie said. He did not choose the traditional optical module track; from day one the company anchored on a wafer-level technology path. NVISION is encouraged that China's national IC strategy also lists compute-in-memory (breaking the memory wall), 3D integration / 3D stacking (chiplets, hybrid bonding), and optoelectronic convergence (silicon photonics, CPO co-packaging) as core differentiated paths beyond Moore's Law.
Nie noted that most silicon photonic chips on the market rely on overseas foundries, whereas NVISION decided from the start to build on domestic capabilities and industrialize together with the domestic value chain. The team has extensive 0-to-1 industry experience and a sharp view of products and industrialization — Intel itself was the first platform to mass-produce heterogeneous integration, and that experience taught the team what "volume production" really means. Photonics has a long history and, like CMOS large-scale ICs, has developed for more than 60 years, yet the scale of optical communications remains far smaller than the CMOS ecosystem.
"Future OIO will inevitably move toward hybrid and heterogeneous integrated optical interconnect. Our core is wafer-level optoelectronic heterogeneous integration and advanced packaging," Nie has repeatedly stressed. He believes next-generation optical interconnect is no longer a simple optical-module form factor; it must be developed with a semiconductor mindset, grounded in Moore's Law, and iterated toward higher density. NVISION's core also aligns with national strategy, with silicon photonic chips, high-speed optical devices, and advanced 2.5D/3D optoelectronic co-packaging as its technology base. To support this positioning, NVISION has partnered with multiple silicon photonics process platforms and advanced packaging platforms. The company now has a three-city footprint — Shanghai (R&D and operations), Xi'an (R&D), and Suzhou (R&D and industrialization) — and is deeply involved in drafting China Mobile's DORA open standard for reconfigurable optical interconnect.
Commercial Progress: 1.6T PIC / 3.2T NPO in Sampling; 6.4T CPO in Development
At this CIOE, NVISION showcased its full product matrix, including silicon photonic PIC chips, NPO/CPO optical engines, WDM light-source chips, and OIO optical engines — a complete ladder of solutions from today to the next generation.
1.6T silicon photonic PIC: Already in sampling, with clear customer demand. Nie acknowledged that overseas wafer capacity for 800G/1.6T silicon photonic PICs is constrained, and domestic capacity has not yet fully ramped — a challenge for domestic silicon photonics wafer supply. But NVISION has its own design and process-development capabilities and partners with silicon photonics foundries, so planned capacity is relatively large. After 1–2 years of integrating domestic process and design, small-volume production has begun this year; next year domestic wafer volumes can reach tens of thousands of wafers, and the domestic supply chain will formally scale.
3.2T NPO: Preparing for sampling. The NVISION team sees clear market demand for NPO. Using 2D/2.5D packaging, NPO offers a compromise between pluggable and co-packaged approaches and has become a customized solution for many CSPs.
6.4T CPO optical engine: Still in packaging and R&D. Nie positions it as "the first truly meaningful 3D package," substantially raising bandwidth density, with samples expected in Q1 2027.
Behind the three product lines is NVISION's firm embrace of domestic silicon photonics platforms and advanced packaging. He said domestic silicon photonics is iterating quickly, and performance, capacity, and reliability are core competitive advantages.
NPO, CPO, and OIO Are Not in Conflict: Market Relationships and NVISION's Place
There is much debate over the future of OIO, CPO, and NPO. Nie's judgment is direct: the three paths do not conflict.
NPO: Over the next 3–5 years it will become a mainstream solution in China and even overseas, with greater opportunity especially in scale-up scenarios. Nie argued that pluggable solutions' disadvantages in density and power leave room for NPO as a compromise — without deeply changing system architecture the way CPO does, while still delivering clear gains in density and power.
CPO: Needs to be packaged together with GPUs and HBM. Nie believes NVIDIA's choice of CPO fits because NVIDIA's system architecture is GPU-centric high-density integration. NVISION provides the engine solution — essentially silicon photonics plus 3D advanced packaging.
OIO: Higher density and stricter bandwidth needs between chips. Nie sees OIO as the natural evolution after NPO and CPO, to be realized step by step through accumulation on silicon photonics plus 3D packaging platforms.
NPO and CPO share the same core but differ in packaging form. Both are essentially silicon photonics plus advanced packaging; the difference lies in packaging hierarchy and coupling to compute chips. NVISION's commercial opportunity is to supply silicon photonic chips and optical engine capabilities across all three paths, rather than betting on a single route.
Wafer-Level Heterogeneous Integration: China and Overseas Still on the Same Starting Line
NVISION's core technology is wafer-level heterogeneous optoelectronic convergence — leveraging CMOS lines for scalable manufacturing and integrating compound optical chips with silicon-based electrical chips at the wafer level. For NVISION, the lasting value is making hybrid/heterogeneous integration more aligned with Moore's Law.
He explained that lasers were once a niche industry, but in the OIO era thousands or even hundreds of millions of chips will sit on the same advanced packaging platform. How to integrate more deeply and raise bandwidth rates exponentially is the fundamental problem wafer-level heterogeneous integration must solve. On a 5- to 10-year horizon, whether silicon photonic PICs, light-source chips, or electrical chips, all must move toward higher integration.
Are China and overseas at the same level? Nie said this must be viewed by approach.
First, on light-source heterogeneous integration, aside from Intel there has been little further progress in China, closely tied to the ecosystem: Intel integrated InP onto silicon photonics platforms, and China still has a gap. Reasons include: (1) concerns about laser reliability and failure; (2) limited experience and investment; (3) Intel is not a foundry and lacks broader industry partners of that kind.
Second, China has its own opportunities in heterogeneous integration — for example, silicon-based lithium niobate integration may move faster domestically.
Third, overseas will move faster on hybrid/heterogeneous integration architectures such as CoWoS or COUPE, using advanced packaging to integrate optics and electronics heterogeneously onto one chip in 3D. But China is investing heavily in silicon photonics foundry and advanced packaging platforms, so NVISION's path is silicon photonics as the base, topped with 3D packaging.
"Next year and the year after, China may see major breakthroughs and may carve out distinctive directions," Nie said. He also stressed the need for system-level collaboration with electrical-chip and system vendors; how system architecture and design fit together is more critical than any single device.
The Shortfall in Domestic OIO Is Not Manufacturing, but System-Architecture Understanding
On domestic OIO progress, Nie did not focus on manufacturing capability but on a dimension often overlooked: "OIO is not just a device problem; it is a system-architecture problem. We cannot only stare at the optical engine itself; we should take part in defining data-center network architecture." That is the deeper reason NVISION actively joins drafting China Mobile's DORA open standard for reconfigurable optical interconnect.
Nie noted that NPO and CPO standards are already fragmenting; the next generation may be even more diverse. Defining OIO hinges on how it works with GPUs, switches, and system architecture.
"Large-model vendors may define data-center architecture, so we hope to work more with system vendors, cloud providers, GPU vendors, and switch vendors to land next-generation network architectures in ways that better fit domestic needs," he added.
Technically, WDM may be used to address OIO density: as single-channel rates approach physical limits, multiplexing multiple wavelengths on one fiber is a key way to raise bandwidth density. But how many wavelengths, what channel spacing, what rate per wavelength, and how optical switches are configured are not decisions device vendors can make alone — they are set by network topology and traffic models.
Opportunities for domestic firms: a large enough market, rich application scenarios, and a rapidly maturing domestic supply chain. The challenge: forming coordination across devices, packaging, and systems rather than fighting separately.
Optoelectronic Convergence: Near-Term Path and Long-Term Fusion
Multiple sources show NVISION's conviction in optoelectronic convergence and CMOS process routes. Yet today's product forms focus on optics. How will optoelectronic convergence be realized?
Nie explained several meanings of CMOS process for NVISION: first, silicon photonics itself is a form of fused CMOS process; second, the company stacks 3D packaging on silicon photonics. These two layers form NVISION's technology base for optoelectronic convergence.
On the path: there is industry division of labor — systems, optics, and electronics each have strengths. In the near term, NVISION will partner with electrical-chip vendors to open up optoelectronic interfaces.
Longer term, the OIO era will feature diverse network architectures, and EIC (electrical IC) plus PIC (photonic IC) will need deeper fusion. When bandwidth-density demand is pushed to the extreme, the physical boundary between optics and electronics blurs; the two must integrate deeply at the packaging level and even at the chip level.
NVISION — The Name
At the end of the interview, I asked a lighter question: How did the name NVISION (Yingweixin) come about?
Nie smiled. At founding, the team considered many names. The English "VISION" came first — also the company vision: optoelectronic convergence bringing the next Moore's Law. The "N" can mean New, or a new direction built from Intel integration experience.
"A new Vision," Nie said. It is both the company name and his judgment of the industry.
The Chinese name carries several layers: he and teammates once led silicon photonics programs at Intel and understand optical interconnect deeply; the team believes optoelectronic convergence is the future; and the character "芯" (chip/core) signals the resolve to redefine optical interconnect with a semiconductor mindset.
For next-generation optical interconnect, NVISION chose a long path: starting at wafer level, integrating optics and electronics at the deepest layer. Whether that path succeeds depends on technology, supply chain, system ecosystem, and time. But the direction, at least, is already clear.
Optoelectronic convergence bringing the next Moore's Law — that is NVISION's answer, and the answer the whole industry is seeking.
